---------------------------------------------------------------------------------
  -- Design Name : Register Write-Back Stage
  -- File Name   : WbStage.vhd
  -- Function    : Register write-back stage
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity WbStage is
  port (
    clk         : in  std_logic;
    wrkIn       : in  std_logic;
    wrkOut      : out std_logic;
    op          : in  opCode;
    aluOut      : in  word32;
    DDBus       : in  word32;
    stackOut    : in  word32;
    rd          : in  regAddr;
    wbData      : out word32;
    wr          : out std_logic;
    rwr         : out regAddr;
    rwr16       : out std_logic;
    loRts       : out std_logic   
  );
end WbStage;

architecture behavioral of WbStage is
  signal raddr:    regAddr;
  signal wbSel:    std_logic_vector(1 downto 0);
--  signal clock:    std_logic;
begin

  rwr <= rd;
--  clock <= clk and wrkIn;
  wrkOut <= wrkIn;
  
  wbMux : GenMux32_4 port map (
    in1       => aluOut,
    in2       => DDBus,
    in3       => stackOut,
    in4       => (others => '0'),
    sel       => wbSel,
    muxOut    => wbData
  );
  
  control: WbCtrl port map (
    op        => op,
    wbSel     => wbSel,
    wr        => wr,
    rwr16     => rwr16,
    loRts     => loRts
  );

end architecture behavioral;